The present invention relates to a semiconductor design technology, and more particularly to a leakage current deterring circuit and internal voltage generating circuit using the same semiconductor memory device. The internal voltage generating circuit is capable of generating a back bias voltage based on a target level changed according to a leakage current of the semiconductor memory device.
Semiconductor memory devices such as a dynamic random access memory (DRAM) use a capacitor as a unit element for storing data, which is called a cell.
In order to store a logic high level of data ‘1’, a relatively high level of voltage is provided to the cell and a high level of potential is maintained in the cell. On the contrary, a relatively low level of voltage is provided to the cell, maintaining a low level of potential in the cell for storing a logic low level of data ‘0’.
Each cell of the semiconductor memory device further includes a MOS transistor connected to the capacitor. The MOS transistor performing a switching operation. That is, when the MOS transistor turns on, the corresponding cell is coupled to a bit line and potential corresponding to data stored in the cell is shared to a bit line.
When the MOS transistor turns off the cell is disconnected to the bit line and potential of the cell is stored as data. In case that the capacitor provided in the cell is ideal, the potential, i.e., charge, is maintained to a constant level. However, an actual capacitor loses the stored charge due to a leakage current with time. Accordingly, it cannot be distinguished whether the stored data is in a logic high level or a logic low level. In regard to the kind and cause of the leakage current, it will be described below in detail.
FIG. 1 illustrates a cross-sectional view of a transistor provided in a semiconductor memory device such as a DRAM, which shows a leakage current generally caused in the DRAM.
Referring to FIG. 1, as mentioned above, it is a cross-sectional view of a NMOS transistor connected to a plurality of cells in the DRAM for operating as a switch. The NMOS transistor is composed of a source, a drain and a gate. The source and drain are metallic contact terminals connected to an N-type semiconductor. The gate, which is also a metallic contact terminal, is coupled to a substrate through an isolating material. The substrate is a P-type semiconductor and is connected to a well bias, which is another metallic contact terminal. Generally, in such NMOS transistors, the drain is connected to the cell; the gate is connected to a word line; and the source is connected to a bit line.
Accordingly, when the word line is activated, the gate is supplied with a boosted voltage VPP. That is, the NMOS transistor turns on. A channel is formed on the substrate and the cell connected to the drain is coupled to the bit line connected to the source. Therefore, the drain and source each have an identical level of voltage as each other, i.e., a core voltage VCORE or a ground voltage VSS.
On the contrary, when the word line is inactivated, the gate is supplied with the ground voltage VSS. That is, the NMOS transistor turns off. The channel disappears on the substrate and the cell is disconnected to the bit line. The drain is supplied with a voltage stored in the cell and the source is supplied with a bit line precharge voltage VBLP generated by a precharge operation. If the voltage stored in the cell is relatively high level, the core voltage VCORE is supplied to the drain. If the voltage stored in the cell is relatively low level, the ground voltage VSS is supplied to the drain.
Among the above mentioned conditions of the NMOS transistor, there is a leakage current in case that the NMOS transistor turns off. The leakage current is classified into an off leakage current I_IOFF and a junction leakage current I_LEAK which are caused in case that the NMOS transistor turns off and the core voltage VCORE is supplied to the drain. The off leakage current I_IOFF is a current generated between the drain supplied with the core voltage VCORE and the source supplied with the bit line precharge voltage VBLP. The junction leakage current I_LEAK is a current generated between the drain supplied with the core voltage VCORE and the substrate supplied with the back bias voltage VBB.
Accordingly, a total leakage current I_TOTAL caused in the cells of the DRAM is the sum of the off leakage currents I_IOFF and the junction leakage currents I_LEAK.
Herein, the off leakage current I_IOFF is generated by level difference between the core voltage VCORE and the bit line precharge voltage VBLP, generally the core voltage VCORE being twice as high as the bit line precharge voltage VBLP. The gate width has also an effect on the amount of the off leakage current I_IOFF.
The junction leakage current I_LEAK is a kind of reverse saturation current. It is generated because the drain is an N-type material and the substrate is a P-type. The amount of the junction leakage current I_LEAK is negligible compared with the off leakage current I_IOFF.
Therefore, in order to reduce the total leakage current I_TOTAL caused in the plurality of cells of the DRAM, it is more effective to reduce the off leakage current I_IOFF than the junction leakage current I_LEAK.
As described above, the gate width has an effect on the amount of the off leakage current I_IOFF. The off leakage current I_IOFF is in inverse proportion to the size of the gate with. It may be considered lengthening the gate width of the NMOS transistor to reduce the off leakage current I_IOFF. However, it is not consistent with the trend whereby DRAM is being integrated and reduced in size more and more.
Another method is used where a back bias voltage VBB that is lower than a ground voltage VSS is supplied to the substrate of the NMOS transistor. The off leakage current I_IOFF can be reduced by increasing the amount of charges in a depletion layer, the depletion layer being formed in a substrate region between the drain and the source. This method is used in most of the DRAM for the integration and the miniaturization because it can reduce the off leakage current I_IOFF without increasing the size of the DRAM.
As the back bias voltage VBB applied to the substrate increases more in a negative direction of which level is lower than the ground voltage VSS, the amount of charges in the depletion layer increases more. In addition, the junction leakage current I_LEAK increases in proportion to the amount of charges. The reason is that the junction leakage current I_LEAK is a reverse saturation current which has a characteristic to increase in proportion as the amount of charges in the depletion layer increases.
Accordingly, the junction leakage current I_LEAK, which has almost a zero value when the back bias voltage VBB is close to the ground voltage VSS, increases as the back bias voltage increases in the negative direction. After a given time, the junction leakage current I_LEAK becomes bigger than the off leakage current I_IOFF which decrease according to the level of the back bias voltage VBB. After all it causes such a problem that the total leakage current I_TOTAL increases by the back bias voltage VBB which is for reducing the total leakage current I_TOTAL.
FIG. 2 is a graph illustrating the interrelation between the back bias voltage and the leakage current in the DRAM.
Referring to FIG. 2, it is illustrated how the off leakage current I_IOFF and the junction leakage current I_LEAK change according to a level change of the back bias voltage VBB applied to the general DRAM.
At the time when the back bias voltage VBB is close to the ground voltage VSS, the off leakage current I_IOFF has a relatively big value and the junction leakage current I_LEAK has a very small value which is almost a zero. Thereafter, as the back bias voltage VBB increases in the negative direction, the off leakage current I_IOFF decreases and the junction current I_LEAL gradually increases. However, the total leakage current I_TOTAL decreases in period of {circle around (1)} because the decreasing width of the off leakage current I_IOFF is bigger than the increasing width of the junction leakage current I_LEAK.
When the back bias voltage become a predetermined level, the increasing junction leakage current I_LEAK and decreasing off leakage current I_IOFF become identical to each other. Starting from the point {circle around (2)}, the levels of the junction leakage current I_LEAK and the off leakage current I_IOFF are reversed. That is, the total leakage current I_TOTAL of the DRAM, which has decreased according to the decreasing back bias voltage VBB, begins to increase.
If the back bias voltage VBB continuously increases in the negative direction thereafter, the total leakage current I_TOTAL increases accordingly more and more, referring to the period of {circle around (3)}. In order that the total leakage current I_TOTAL has the smallest value, the level of the back bias voltage VBB should be the level when the levels of the junction leakage current I_LEAK and the off leakage current I_IOFF are reversed
However, even if manufactured through the same process, the DRAMs do not have the identical characteristics due to the various environmental factors. That is, in each of the DRAMs generated through the same process, the level of the back bias voltage to make the total leakage current I_TOTAL have the smallest value may be different, but generally it is determined between the level of −0.7 voltage and the level of −0.9 voltage. After all, it is most important to generate an appropriate back bias voltage VBB in order to reduce the total leakage current I_TOTAL of the DRAM.
FIG. 3 is a block diagram of a conventional back bias voltage generator. Referring to the FIG. 3, the back bias voltage generator 300 includes back bias voltage detector 302 and a voltage generator 304.
The back bias voltage detector 302 generates a detecting signal VBB_DET according to the level of the back bias voltage VBB. The voltage generator 304 generates the back bias voltage VBB in response to the detecting signal VBB_DET.
Herein, the voltage generator 304 includes an oscillating unit 3042 and a pumping unit 3044. The oscillating unit 3042 generates an oscillating signal OSC, which is toggled in a period determined according to the detecting signal VBB_DET. The pumping unit 3044 generates the back bias voltage VBB by pumping charges in response to the oscillation signal OSC.
The operation of the conventional back bias voltage generator will be described below based on the above configuration.
The back bias voltage detector 302 compares the level of the back bias voltage VBB with a target level and determines the level of the detecting signal DET_VBB according to the comparison result. And then, the oscillating unit 3042 generates an oscillating signal OSC that is toggled in a period determined according to the level of the detecting signal VBB_DET. The pumping unit 3044 pumps the charges in response to toggling of the oscillating signal OSC, to thereby generate the back bias voltage VBB.
For example, when the back bias voltage VBB is higher than the target level, the back bias voltage detector 302 outputs the detecting signal VBB_DET in a logic high level. Accordingly, the oscillating unit 3042 generates the oscillating signal OSC toggled in a predetermined period. The pumping unit 3044 pumps the charges in response to toggling of the oscillating signal OSC, to thereby decrease the back bias voltage to have the target level.
FIG. 4 is a schematic circuit diagram of the back bias voltage detector described in FIG. 3.
Referring to FIG. 4, the back bias voltage detector 302 includes PMOS transistors and an inverter. First and second PMOS transistors P1 and P2 are connected in series between a core voltage VCORE terminal and a ground voltage VSS terminal. The inverter INV drives a voltage on a connection node DET of the first and second MOS transistors P1 and P2 to thereby generate the detecting signal VBB_DET.
Herein, the first PMOS transistor P1 controls to connect the core voltage VCORE terminal and the connection node DET, which are respectively connected to a source and a drain thereof, in response to the ground voltage VSS received from a gate thereof. The second PMOS transistor P2 controls to connect the connection node DET and the ground voltage VSS terminal, which are respectively connected to a source and a drain thereof, in response to the back bias voltage VBB received from a gate thereof.
The operation of the back bias voltage detector 302 will be described below based on the above configuration.
Based on a resistance of the first PMOS transistor P1 which is determined by the ground voltage VSS, a voltage level on the connection node DET is determined in response to a resistance of the second PMOS transistor P2 which changes according to the back bias voltage VBB. The voltage on the connection node DET is driven to a logic high or low level based on a logic threshold voltage level of the inverter INV and outputted as the detecting signal VBB_DET.
For example, when the back bias voltage VBB increases in a negative direction of which level is lower than the ground voltage VSS, the resistance of the second PMOS transistor P2 decreases. Accordingly, the voltage on the connection node DET decreases. When the voltage on the connection node DET becomes lower than the logic threshold voltage level of the inverter INV, the inverter INV outputs the detecting signal VBB_DET in a logic high level.
Accordingly, the conventional back bias voltage detector 302 can change the target level of the back bias voltage VBB by changing the sizes of the first and second PMOS transistors P1 and P2. After the target level is firstly determined, the sizes of the first and second PMOS transistors P1 and P2 are controlled to make a transition of the logic level of the detecting signal VBB_DET at the timing corresponding to the determined target level.
However, after the sizes of the first and second PMOS transistors P1 and P2 are determined once at the design stage, the conventional back bias voltage detector 302 cannot change the target level. Accordingly, a plurality of DRAMs should have an identical target level.
That is, the level of the back bias voltage wherein the least total leakage current I_TOTAL is caused in some of the DRAMs generated through the process is determined as the target level. The target level is applied to all of the DRAMs generated through the process in the lump.
Through the conventional method, the determined back bias voltage VBB makes the total leakage current I_TOTAL at the smallest level in some of the DRAMs. However, in the other DRAMs, the total leakage current I_TOTAL may reach to the smallest level or not at the determined back bias voltage VBB. In that case, the amount of the loss of cell charges increases by the leakage current generated in a standby state. The refresh period of the DRAMs is reduced, thereby causing problems such as a refresh fail.